Freescale Semiconductor /MKW21Z4 /XCVR_PHY_REGS /CFG2

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Interpret as CFG2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PHY_FIFO_PRECHG 0 (RFU03)RFU03 0 (RFU04)RFU04 0 (RFU05)RFU05 0 (RFU06)RFU06 0X2_DEMOD_GAIN 0 (RFU07)RFU07 0 (RFU08)RFU08 0 (RFU09)RFU09 0 (RFU10)RFU10 0 (RFU11)RFU11 0 (RFU12)RFU12 0 (RFU13)RFU13 0 (RFU14)RFU14 0 (RFU15)RFU15 0 (RFU16)RFU16 0 (0)PHY_CLK_ON

PHY_CLK_ON=0

Description

PHY CONFIGURATION REGISTER 2

Fields

PHY_FIFO_PRECHG

PHY FIFO Precharge Level

RFU03

Reserved for future use.

RFU04

Reserved for future use.

RFU05

Reserved for future use.

RFU06

Reserved for future use.

X2_DEMOD_GAIN

X2_DEMOD_GAIN

RFU07

Reserved for future use.

RFU08

Reserved for future use.

RFU09

Reserved for future use.

RFU10

Reserved for future use.

RFU11

Reserved for future use.

RFU12

Reserved for future use.

RFU13

Reserved for future use.

RFU14

Reserved for future use.

RFU15

Reserved for future use.

RFU16

Reserved for future use.

PHY_CLK_ON

Force PHY Clock On (testmode)

0 (0): PHY clock is enabled by TSM output: rx_phy_en

1 (1): PHY clock is forced on at all times

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